Many of today's integrated circuit (IC) designs consist of a complete system on a chip (SOC). An SOC integrates multiple pre-designed and reusable circuits, termed “cores,” onto a single integrated circuit. This integration allows SOC manufacturers to reduce design time and lower production costs. A basic SOC 10 containing multiple embedded cores is shown schematically in FIG. 1. Multiple cores 14 are embedded in the SOC 10. The cores 14 may comprise processor cores, memory cores, or logic cores. Each core has a number of core terminals or pins 16 that provide access to the internal circuitry of the core. Similarly, the SOC 10 has a number of integrated circuit or SOC terminals or pins 12 that provide access to the internal circuitry of the SOC and the multiple cores.
The time required to effectively test an SOC, which requires the separate testing of each individual core, is a major factor in overall production time. Therefore, as SOCs are produced with greater and greater levels of circuit density, efficient testing schemes that guarantee high fault coverage while minimizing test costs and chip area overhead are essential.
The cores of an SOC are typically tested using a number of structured “design-for-testability” (DFT) techniques. These techniques rest on the general concept of making all or some state variables (memory elements like flip-flops and latches) directly controllable and observable. If all state variables can be controlled or observed, a core can be treated for testing purposes as a combinational network. The most frequently used DFT methodology is based on using scan cells located internally within the core to form internal scan chains. A core that has been designed for testing according to this methodology is known as a “scan circuit” and has two modes of operation: a normal mode and a test mode. In the normal mode, the memory elements of the scan cells are configured to couple with the combinational logic of the core and perform their normal functions. In the test mode, the scan cells operate in multiple submodes that utilize test patterns to test the functional paths of the combinational logic. The most basic scan cell operates in at least two submodes: scan and capture. In the scan submode, the memory elements of the scan cells are configured to couple with one another to form shift registers called “scan chains.” A set of test patterns may then be shifted into the scan chains. During the capture submode, the scan cells are briefly decoupled from one another and operate in their normal mode, thereby launching the test patterns through the functional paths of the combinational logic. The responses are then captured in various memory elements of the core, which usually include memory elements of the scan cells. The scan submode may then be repeated in order to shift the test responses out of the scan chains and simultaneously shift the next test patterns in. The test responses are then compared to fault-free responses to determine if the core-under-test (CUT) operates properly. In contrast, a core that does not have internal scan chains, a “non-scan circuit,” is tested by providing test patterns to the core's inputs and reading the results at the core's outputs.
In order to test a core of an SOC, a connection must be provided between the core pins and the SOC pins. This connection is provided by one of several test access mechanisms (TAMs). The major types of TAMs include: parallel access (multiplexed access), serial access, and test bus access.
Parallel access to the core pins is achieved by using SOC pins exclusively dedicated to the core pins or by using shared SOC pins connected to multiple core pins through multiplexers. The advantage of this method is that the core can be tested as if it was stand alone, using previously created test patterns applied directly to the core. The disadvantages, however, are the pin requirement and the high area costs that result from routing and multiplexing overheads.
Serial access can be achieved using a number of different techniques. One such technique for achieving serial access to the core pins is to use scan chains positioned around the core and configured to access the individual pins of the core. This type of scan chain is typically referred to as a “wrapper” scan chain. Although a wrapper scan chain may be accessed with just two pins, thereby reducing the number of pins required to test a core, use of a wrapper scan chain may result in a corresponding increase in test application time due to the time required to shift patterns into and out of the scan chain.
Various schemes using buses for connecting the core pins with the SOC pins have also been used, often in combination with the parallel and serial access methods discussed above. One method involves the use of dedicated on-chip variable-width buses for propagating test data signals. Control signals are generated from an on-chip controller to control the configuration of test wrappers around the cores that provide paths between test buses and core terminals. Another technique using a test bus involves building a test “shell” around each core. Each test shell contains a local n-bit-wide test “rail”. The test shells, which operate like wrapper scan chains, can be set to function mode, IP test mode, or bypass mode based on control signals. At the SOC level, global test rails are also built to connect different local test rails in different cores or to connect local test rails to SOC pins to obtain a flexible and scalable test bus architecture. Additionally, an “addressable test access port” architecture has been proposed that provides serial and parallel communication paths between each core and the SOC pins.
Testing of SOC cores further requires the creation of a carefully designed test schedule. The test schedule controls how and when the core pins should be accessed from the SOC pins via the test access mechanism. Because the test schedule affects the time required to test the SOC, it is an important consideration in reducing overall chip test time. Although several methodologies for scheduling the testing of cores have been developed, all suffer from some limitations. Most scheduling techniques, for instance, assume that a particular TAM of a fixed type and size is used during testing. These techniques are of limited applicability and do not offer a flexible approach to the test scheduling problem. Other techniques consider the scheduling problem in terms of groups of SOC pins. These techniques are also inflexible and do not allow the SOC pins to be freely associated with the cores being tested. Still other techniques do not consider the possibility of concurrent core testing. Concurrent core testing, however, allows unused resources to be utilized, thereby optimizing test scheduling. Further, most techniques do not consider the peak power used in a core test as a relevant constraint on test scheduling. Peak power limitations, however, are important considerations and may cause damage to the SOC if ignored. Although some techniques do consider peak power as a relevant constraint, none allow peak power to be considered as an integral part of the scheduling problem.